It is known that during switching between two digital signals of the same character, which are received with a different phase, the resultant jitter transient must be kept within the amplitude and frequency limits which are predetermined by the international recommendation (recommendation G. 703 of CCITT) to secure the desired quality of the resultant digital signal downstream of the switching operation.
An already known solution to this problem is to utilize the alignment word of the received digital signal prior to switching for synchronizing the freqeuency of the clock signal of the digital signal downstream of the switch.
This solution theoretically avoids the jitter transient of the digital signal during the switching transient, but involves the use of an alignment word detection circuit which is rather complex to provide.